Electronic devices have become pervasive in our household equipment, our cars, our communication tools and indeed in almost every object that surrounds us in our private and professional spheres. Not only do they multiply, but they continue to decrease in size, to use less energy and cost less. To assemble such devices, the semi-conductor industries have perfected silicon-based technologies. However, they will soon be approaching the physical limits of solid state physics. To go beyond this barrier, they are already working on new approaches for nanometric level electronics.
In order for a mobile phone to transmit a call, it must first possess an analogue-digital (AD) convertor, transposing voice pressure and frequency changes into a digital signal, also an antenna, a microphone, an amplifier, an on-board communication system… inter alia. And to accommodate all the “apps” that the user has downloaded, the mobile must incorporate an accelerometer, a graphic processor, a video processor, lots of memory, etc. All these functional electronic components must be miniaturized as far as possible so as not to make the phone unwieldy, that it consumes the least energy possible to save the battery, to dissipate heat efficiently to avoid the phone heating up and of course, all of this costing only a few cents to make and assemble!
Semi-conductor manufacturers are faced with a seemingly endless increase in challenging demands for electronic components for the automobile sector, health applications, or with the advent of connected objects. They must strike a balance between the race to miniaturize and avail of low energy ratings with an exponential growth of the costs for setting up production line infrastructures.
Of course they receive help via Moore’s law (a prediction made by Gordon Moore, one of the co-founders of Intel Corp., who asserted that the number of transistors on a chip would double up every decade). The law applies to chips – with integrated circuits (ICs) photo-engraved on the silicon wafer. But obviously, to increase the numbers, viz., the density of transistors, their individual size must decrease as must the engraving (i.e., the groove width). The size of an engraved groove went under the micron or micro meter and progressively narrowed down to 1 nm, 3 orders of magnitude lower! Today most engravings are between 180 nm, 65 nm or 45 nm. Very few sites in the world (Intel, IBM, TSMC or Samsung) have the capacity to mass-produce engravings at 20, 22 or even 14 nm.
The race to miniaturize devices raises new and serious challenges for industrialists. “For the past 50 years, the entire semi-conductor sector has been based on a form of transistor called the MOS (metal on silicon), photo-engraved on solid state silicon wafers. But Moore’s law also tells us that we shall one day reach the limits for transistor function, at around 20 nm, viz., the physical dimension at which it will no longer be possible to optimize the behaviour of the transistor circuit itself, i.e., attain an optimum between performance and gate leakage,” explains Joël Hartmann, Executive Vice-President STMicroelectronics and responsible for the fabrication and technological R &D for on-board systems. “Currently we have solutions that allow us to go below the 20 nm bar, to optimize our transistor performance levels while limiting gate leakage.” That would, in essence, take us beyond the barriers of Moore’s law!
Naturally, it will take some time before world production reaches scales likes these. But given the lead times needed for design, development, testing and certification of prototype devices and especially in view of the time and cost to build and prepare the necessary plant facilities, likewise to carry out production adjustments and set production lines in motion, it will be wise to anticipate. To illustrate, we can note that Intel Corp took 15 years to industrialize its 22 nm standard engraving process and launch mass production.
This new challenge accompanies a constantly growing market demand. The consultant group Gartner has noted that world sales of semi-conductors has progressed by 5% in 2013 for a market value of 315 billion $US (approx. 240 billion euros). The semi-conductor market is no longer limited to computer devices and consumer electronics. The pervasiveness of mobile phones, the growing fraction of electronics in sectors such as the automobile industries and health care, together with the advent of connected objects – where it is expected there will be some 50 billion units functioning by 2020 and for which no application can escape – signals the fact that an ever larger fraction of the world’s economy needs semi-conductors.
In order to meet these needs, the industrialists are prepared to make ever increasing plant design and construction investments. Each new generation of factory costs the double of the preceding site. Current projects on the board are estimated at 5 billion $US apiece and it is thought 10 billion $US will be needed to build a new assembly line in 2020. This encourages the major groups to consolidate and share necessary investments. “To date, industrialists were identified with their specific technologies. Tomorrow, there will probably be a single technological base, a single micro-electronic base, akin to what happened with internal combustion engines for cars; the various actors will be differentiated by their applications, their markets, their clients,” foresees Jean Fompeyrine, who directs the research at IBM’s Advanced Functional Material Research Lab in Zurich.
Europeans will be caught up by this trend. Early 2014, a certain number of the sector’s chairmen and CEOs created the Electronics Leaders Group (ELG) to apply leverage and pressure on the European Commission so that it continues to pursue the ambitious strategy announced for this field. Their stated objective is to see Europe become a major actor in micro-electronics by doubling current local component production by 2020 and creating, in parallel, some 250,000 associate jobs. The problem here is that this presupposes that EC rules be made more flexible, especially when it comes to public funding and aid grants. Those enterprises who consider they are limited by regulations today are planning to set up shop in non-EC countries who will offer subsidies and significant fiscal advantages.
The formula the market place has to solve can be summarized as follows: how can we manufacture and assemble sufficient volumes of chips as powerful as a complete computer from a few years back, for just a few cents each, while taking note that the complexity needed also continues to increase endlessly, while the number of actors in the field decreases with a market place increasingly demanding in terms of available on-board functions?
Solutions forthcoming for this equation relate to several aspects of chip fabrication, beginning with the silicon wafers. The silicon semi-conductor material is smelted and moulded into a cylindrical shape, then sliced, each wafer being only a few hundred microns thick. It is on these sliced substratewafers that the complex integrated circuits are photo-engraved. We can note that the diameter of the wafers has risen progressively from 150 mm to 200 mm and to 300 mm in diameter. The bigger the diameter, the more circuits can be engraved at a time, and this decreases the price per slice. One technical option currently explored is to increase wafer diameter to 450 mm. Such a move, if successful, would lead to a cost decrease of approx. 30% but also supposes that all the production equipment be adapted to the new figures. Although the project was launched enthusiastically several years ago, i.e., to mass produce 450 mm silicon slabs, it slowed down considerably when several analysts pointed out that the cost for the new equipment would carry a price tab in excess of 12 to 14 billion $US …
Another stumbling block is that today’s photo-engraving equipment does not normally allow you to engrave to less than 10nm accurately, or can just be done, but for a prohibitive cost. One technology, called Extreme UV (EUV), under development, will no doubt replace traditional photo-engraving. It uses 13 nm wavelength soft X rays (with low energy photons, opposed to hard X-rays). The technology involved consists of bombarding a tin (Sn) target in a vacuum with a close to 1 MW CO2 laser beam. The strike volatilizes the target and leads to emission of X rays at 13 nm wavelength; the latter are captured using mirrors and directed to the silicon wafer. “This represents an extremely complex kind of technology and, for the time being, we simply do not have lasers that powerful, to be included in an industrial, mass-production, environment. Moreover, there is only one company in the world, the Dutch enterprise ASML who are trying to master the technology from an industrial point of view!” explains Joël Hartmann.
The days of silicon devices are not completely over yet. Also, Moore’s Law is not yet outdated. While we await the availability of EUV, industrialists are placing their bets on More Moore; in other words, they are looking for ways push back the barrier set by this law before they even reach its limit. That would correspond to “More Moore.”
The first option is FD-SOI (Fully depleted silicon on insulator). This particular technology was developed in France jointly by Soitec – who supply the silicon on insulator wafers, ST Microelectronics and CEA-Leti. The principle is to use a substrate covered with an insulator layer, which improves the transistor functions while cancelling parasite effects found with solid-state silicon. “A processor built around this technology will be able to perform more operations for one watt power, heating less and therefore drawing less form the battery,” explains Thomas Skotnicki, Director of the STMicroelectronics Disruptive Technologies Programme and one of the ‘fathers’ of FD-SOI technology. STMicroelectronics is currently certifying a series of 28 nm FD-SOI circuits and hopes to launch mass production by early 2015. In mid-May, this technology received the support of Samsung who have decided to adopt it for their components in mobile phones and connected objects, precisely because of the low power consumption factor. “We have a technology here that we can narrow down easily to 10 nm, and go farther still,” asserts Mr. Skotnicki.
The second option lies in FinFETs aka the Tri-Gate device. Developed by Intel Corp., the operation consists of engraving vertical transistors on the steps of silicon slabs only a few nanometers high, and in 3D. The transistors occupy less surface space and gate leakages are reduced. But Tri-Gate technology is even more complicated to implement than FD-SOI and consequently turns out to be more expensive. But Intel Corp. uses it already for its 22 nm photo-engravings in several factories round the world and is now testing feasibility for a 14 nm model. The Taiwanese company TSMC is testing FinFET technology for 20 nm models and mass-production could even begin later this year.
“To go beyond Moore’s Law, four main research axes are being investigated today,” asserts Jean Fompeyrine, listing and commenting them: “First of all, we can envisage changing the transistor structure, as is the case for FD-SOI or FinFET technologies. Secondly, we can replace silicon by some other semi-conductor material in which the electron displacements occur more rapidly, but keeping the basic transistor structure unchanged. The advantage here is that the transistors can be operated at a lower voltage, around 0.5 V, thereby reducing the power consumption of the circuit as a whole. Thirdly, we can substitute for the very function of transistors, i.e., we create a logic base based on some other totally different physical phenomenon. We refer here to tunnel effect transistors (TETs), or to steep slope devices (SSDs) operating just below their threshold value. Fourthly and last research axis, the idea could be to pile up transistors vertically on top of each other, rather than position them side by side. As a result, the density of the transistor circuits would increase but at the same time material adaptations would have to be made to control temperature.”
After that we come to the various alternatives to the element silicon that vary according to the category of components envisaged. Organic electronics – which uses carbon-based molecules, the best known of which is graphene [cf. ParisTechReview article Sept 30, 2013] which will prove highly attractive for opto-electronic applications. It was this technique that led to organic electroluminescent diodes or OLEDs, now appreciated in very high definition TV screens. It can also be used for solar arrays or for field effect transistors (FETs). In photonics, we can have reliable high speed communications among processors and memories, moreover for a low cost, but unfortunately it does not prove efficient for computational work! “These novel technologies are still in their basic conceptual and drawing board stages and not ready, as yet, for technology transfer. It will take years before they move into the industrial sector,” predicts Fabien Boulanger, Director of the Micro-Nanotechnologies unit at the Minalogic Cluster, adding “For one simple reason, viz., with today’s electronics we know how to make perfect connections and /or interfaces, but we do not yet know how to do this with the latest electronic technologies!”
But the real innovation could come in the shape of so-called “quantum dots,” quantum wells and nanoparticles. At the ESPCI [physics and industrial chemistry] ParisTech, following suit to work done at MIT and Berkeley, about 20 years ago, Benoît Dubertret’s research team has been seeking to assemble colloidal nanoparticles to build semi-conductors measuring between several hundred and several thousand atoms. With nanoparticles from small colourful glass flacons the scientists are creating materials with properties that correspond to their physical dimensions. From a cylinder of silicon sliced horizontally and therefore undergoing the laws of solid state physics, they propose to synthesize particles and interconnect them.
Applications run from photovoltaic arrays to organic biomarkers, via electric energy storage, sensors and flay screens “Quantum dots will be the first materials that allow a demonstration that physical and electric parameters relate to the dimensions involved,” says Benoît Dubertret, enthusiastically, “and they hold enormous potential. Thanks to our use of nanoparticles as the building blocks, we can design some really fantastic assemblies,” says Benoît Dubertret.” Another advantage that enhances the attractiveness of quantum dots is that the assemblies can be made on a common lab-top bench. “There will no longer be a need to dispose of white rooms and white factory units that cost a fortune.” Jacques Lewiner, physicist inventor and serial entrepreneur, adds “here we are moving from heavy industries to the joys of pure chemistry!” For this reason alone, Jacques Lewiner foresees the market getting into gear within two years and thereafter displaying a rapid growth rate. Several decades, however, lie ahead before the silicon star fades away definitively, if only to amortize the costly infrastructures built throughout the world in half a century’s history of semi-conductors.