Michel Barreteau obtained his PhD in Computer Science from Versailles University in 1997. His thesis topic dealt with automatic mapping of scientific applications onto parallel machines with the help of a parallelizing compiler (Data Parallelism). Then he continued working at Versailles University as an expert engineer on the iterative compilation for multimedia applications (Instruction Level Parallelism).
He joined Thales Research & Technology in 1999 as a Research Engineer. He first worked on mapping optimization of signal processing applications onto parallel architectures using constraint programming. From 2002 he was responsible of the software development of the SPEAR Design Environment (an implementation tool for mapping of data-intensive signal and image processing applications onto parallel target architectures). He leads, as a Program Manager, several R&T projects whose goals handle tooled-up approaches for efficiently programming dataflow applications on computing intensive embedded systems. He is also responsible of the “High Performance Programming & Tools” research theme and leads a Thales working group about Algorithm Architecture Adequacy.